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Product Description
Sirenza Microdevices' SHF-0189 is a high performance AlGaAs/GaAs Heterostructure FET (HFET) housed in a low-cost surface-mount plastic package. The HFET technology improves breakdown voltage while minimizing Schottky leakage current resulting in higher PAE and improved linearity. Output power at 1dB compression for the SHF-0189 is +27 dBm when biased for Class AB operation at 8V,100mA. The +40 dBm third order intercept makes it ideal for high dynamic range, high intercept point requirements. It is well suited for use in both analog and digital wireless communication infrastructure and subscriber equipment including 3G, cellular, PCS, fixed wireless, and pager systems.
SHF-0189 SHF-0189Z
Pb
RoHS Compliant & Green Package
0.05 - 6 GHz, 0.5 Watt GaAs HFET
The matte tin finish on Sirenza's lead-free package utilizes a post annealing process to mitigate tin whisker formation and is RoHS compliant per EU Product Features Directive 2002/95. This package is also manufactured with green molding * Now available in Lead Free, RoHS compounds that contain no antimony trioxide nor halogenated fire retarCompliant, & Green Packaging dants.
Typical Gain Performance (8V,100mA)
35 30 25 20 15 10 5 0 -5 0 1 2 3 4 5 6 Frequency (GHz) 7 8
Gain, Gmax (dB)
Gmax
* High Linearity Performance at 1.96 GHz +27 dBm P1dB +40 dBm Output IP3 +16.5 dB Gain * High Drain Efficiency * See App Note AN-031 for circuit details
Gain
Applications
* Analog and Digital Wireless Systems * 3G, Cellular, PCS * Fixed Wireless, Pager Systems
Sym bol
D e v ic e C h a r a c t e r is t ic s
( u n le s s o t h e r w is e n o t e d )
T e s t C o n d it io n s , 2 5 C V D S = 8 V , ID Q = 1 0 0 m A
Test F re q u e n c y 0 .9 0 G H z 1 .9 6 G H z 0 .9 0 G H z 1 .9 6 G H z 0 .9 0 G H z 1 .9 6 G H z 0 .9 0 G H z 1 .9 6 G H z 0 .9 0 G H z 1 .9 6 G H z 1 .9 6 G H z
U n its
M in
Typ 2 3 .3 2 0 .1 1 8 .4 1 4 .7 1 8 .6 1 6 .7 40 40 2 7 .2 2 7 .5 3 .2 294 198 -1 .9 -1 7 -2 2 80 -
M ax
Gm ax S
M a x i m u m A v a i la b le G a i n In s e r t i o n G a i n P o w e r G a in
[2 ] [1 ]
Z S= Z S*, Z L= Z L* Z S= Z L= 5 0 O hm s A p p li c a t i o n C i r c u i t
[2 ]
dB dB dBm dBm dBm dB mA mS V V V
o
1 6 .6
2 0 .2
21
G a in O IP 3 P1dB NF ID g V BV BV
SS
204 144 - 3 .0 -
384 252 -1 .0 -1 5 -1 7 8 .0 160 0 .8
O u t p u t T h i r d O r d e r In t e r c e p t P o i n t O u tp u t 1 d B C o m p r e s s i o n P o i n t N o is e F ig u re S a tu r a te d D r a i n C u r r e n t T r a n c o n d u c ta n c e P i n c h - O f f V o lt a g e
[1 ] [2 ]
A p p li c a t i o n C i r c u i t A p p li c a t i o n C i r c u i t A p p li c a t i o n C i r c u i t V V V
DS
=V
DSP
,V
GS
= 0V
m
D
=V S
,V DSP
= - 0 .2 5 V GS
P
D
= 2 . 0 V , ID S = 0 . 6 m A S
GS
G a t e - S o u r c e B r e a k d o w n V o lt a g e G a t e - D r a i n B r e a k d o w n V o lt a g e T h e rm a l R e s i s ta n c e O p e r a t i n g V o lt a g e O p e r a tin g C u rr e n t P o w e r D i s s i p a ti o n
[3 ] [1 ]
[1 ]
IG S = 1 . 2 m A , d r a i n o p e n IG D = 1 . 2 m A , V
GS
GD
= - 5 .0 V
R th V
DS
ju n c t i o n - t o - le a d d ra in -s o u rc e d ra in -s o u rc e , q u ie s c e n t
C /W V mA W
ID Q P
D IS S
[3 ]
[3 ]
[1] 100% tested - Insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test. [2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from sample test measurements. The test fixture is an engineering application circuit board. The application circuit was designed for the optimum combination of linearity, P1dB, and VSWR. [3] Maximum recommended power dissipation is specified to maintain TJ<150C at TL=85C. VDS * IDQ<0.8W is recommended for continuous reliable operation.
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-101240 Rev E
1
SHF-0189 0.5 Watt HFET
Absolute Maximum Ratings
MTTF is inversely proportional to the device junction temperature. For junction temperature and MTTF considerations the bias condition should also satisfy the following expression: PDC < (TJ - TL) / RTH where: PDC = IDS * VDS (W) TJ = Junction Temperature (C) TL = Lead Temperature (pin 4) (C) RTH = Thermal Resistance (C/W)
MTTF @ TJ=150C exceeds 1E7 hours
Parameter Drain Current Forward Gate Current Reverse Gate Current Drain-to-Source Voltage Gate-to-Source Voltage RF Input Power Operating Lead Temperature Storage Temperature Range Power Dissipation Channel Temperature
Symbol IDS IGSF IGSR VDS VGS PIN TL Tstor P DISS TJ
Value 200 1.2 1.2 +9.0 <-5 or >0 200 See Graph -40 to +150 See Graph +165
Unit mA mA mA V V mW C C W C
Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation, the device voltage and current must not exceed the maximum operating values specified in the table on page 1.
Total Dissipated Power (W)
Power Derating Curve
1.50 1.00 0.75 0.50 0.25 0.00 -40 -15
Operational (Tj<150C) ABS MAX (Tj<165C)
87654321 87654321 87654321 87654321 87654321 87654321
1.25
This area not recommended for continuous reliable operation.
10 35 60 85 Lead Temperature (C)
110
135
160
Typical Performance - Engineering Application Circuits (See App Note AN-031)
Freq (MHz) 900 1960 2140 2450 V DS (V) 8 8 8 8 IDQ (mA) 100 100 100 100 P1dB (dBm) 27.2 27.6 27.5 27.3 OIP3* (dBm) 40 40 40 40 Gain (dB) 18.6 16.7 15.2 15.2 S11 (dB) -25 -20 -24 -16 S22 (dB) -13 -8 -14 -14 NF (dB) 4.7 3.2 3.8 3.1
* POUT= +15dBm per tone, 1MHz tone spacing
Data above represents typical performance of the application circuits noted in Application Note AN-031. Refer to the application note for additional RF data, PCB layouts, and BOMs for each application circuit. The application note also includes biasing instructions and other key issues to be considered. For the latest application notes please visit our site at www.sirenza.com or call your local sales representative.
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-101240 Rev E
2
SHF-0189 0.5 Watt HFET
De-embedded S-Parameters (ZS=ZL=50 Ohms, VDS=8V, IDS=100mA, 25 C)
Gain & Isolation
35 30 25 20 15 10 5 0 -5 0 1 2 3 -10 -15 -20 -25 -30 -35 -40 -45 -50 8
Gain, Gmax (dB)
Isolation (dB)
Isolation Gmax Gain
4
5
6
7
Frequency (GHz) S11 vs Frequency
1.0 6 GHz 0.5 2.0 0.5 2.0
S22 vs Frequency
1.0
4 GHz
0.2 3 GHz 8 GHz
5.0
0.2 8 GHz 6 GHz
5.0
0.0
0.2
0.5
1.0
2.0
5.0
inf
0.0
0.2
4 GHz 0.5 3 GHz
1.0
2.0
5.0
inf
2 GHz 0.2 2 GHz 5.0 0.2 1 GHz
S22 5.0
S11 0.5 1 GHz 1.0 1.0 2.0 0.5 2.0
Note: S-parameters are de-embedded to the device leads with ZS=Z L=50. The data represents typical performace of the device. De-embedded s-parameters can be downloaded from our website (www.sirenza.com).
0.35 0.3 0.25
DC-IV Curves
IDS (A)
0.2 0.15 0.1 0.05 0 0 1 2 3 4 5 6 7 8
VGS = -2.0 to 0V, 0.2V steps T=25 C
VDS (V)
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-101240 Rev E
3
SHF-0189 0.5 Watt HFET
Pin Description
Pin #
1 2 3 4
Part Number Ordering Information
Part Number Reel Size Devices/Reel
Function
Gate Source Drain Source RF Input
Description
Connection to ground. Use via holes to reduce lead inductance. Place vias as close to ground leads as possible. RF Output Same as Pin 2
SHF-0189 SHF-0189Z
7" 7"
1000 1000
Mounting and Thermal Considerations It is very important that adequate heat sinking be provided to minimize the device junction temperature. The following items should be implemented to maximize MTTF and RF performance. 1. Multiple solder-filled vias are required directly below the ground tab (pin 4). [CRITICAL] 2. Incorporate a large ground pad area with multiple platedthrough vias around pin 4 of the device. [CRITICAL] 3. Use two point board seating to lower the thermal resistance between the PCB and mounting plate. Place machine screws as close to the ground tab (pin 4) as possible. [RECOMMENDED] 4. Use 2 ounce copper to improve the PCB's heat spreading capability. [RECOMMENDED]
Part Symbolization The part will be symbolized with the "H1" designator and a dot signifying pin 1 on the top surface of the package.
Package Dimensions
.161
3
.016 .177 .068
4
.096
1
2
.019 .118
.041
.059
.015
Recommended Mounting Configuration for Optimum RF and Thermal Performance
Ground Plane
DIMENSIONS ARE IN INCHES
4
Plated Thru Holes (0.020" DIA) SHF-0x89
4
H1
2 3
H1Z
2
1
2
3
1
2
1
Machine Screws
Caution: ESD sensitive
Appropriate precautions in handling, packaging and testing devices must be observed.
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
1
3
3
http://www.sirenza.com
EDS-101240 Rev E
4

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